rggen 0.29.0
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
Gemfile:
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安装:
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Runtime 依赖 (6):
rggen-c-header
~> 0.3.0
rggen-core
~> 0.29.0
rggen-default-register-map
~> 0.29.0
rggen-markdown
~> 0.24.0
rggen-spreadsheet-loader
~> 0.24.0
rggen-systemverilog
~> 0.29.0
Development 依赖 (1):
bundler
>= 0
所有者:
推送者:
作者:
-
Taichi Ishitani
SHA 256 校验和:
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