rggen 0.27.1
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
Gemfile:
=
installieren:
=
Runtime Abhängigkeiten (6):
rggen-c-header
~> 0.2.0
rggen-core
~> 0.27.0
rggen-default-register-map
~> 0.27.0
rggen-markdown
~> 0.23.0
rggen-spreadsheet-loader
~> 0.22.1
rggen-systemverilog
~> 0.27.0
Development Abhängigkeiten (1):
bundler
>= 0
Besitzer:
Pushed by:
Autoren:
-
Taichi Ishitani
SHA 256-Prüfsumme:
=