rggen 0.27.1

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Gemfile:
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instalar:
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Versões:

0.35.2 July 21, 2025 (16 KB)
0.35.1 June 01, 2025 (16 KB)
0.35.0 February 19, 2025 (16 KB)
0.34.0 January 23, 2025 (16 KB)
0.33.4 November 28, 2024 (16 KB)
0.27.1 August 21, 2022 (15,5 KB)

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Runtime Dependencies (6):

rggen-c-header ~> 0.2.0

rggen-core ~> 0.27.0

rggen-default-register-map ~> 0.27.0

rggen-markdown ~> 0.23.0

rggen-spreadsheet-loader ~> 0.22.1

rggen-systemverilog ~> 0.27.0

Development Dependencies (1):

bundler >= 0

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Donos:

Pushed by:

Autores:

Taichi Ishitani

SHA 256 checksum:

Total de downloads 116.606

Desta versão 725

Versão lançada:
August 21, 2022 3:18pm

Licença:
MIT

Versão Requerida do Ruby: >= 2.6

New versions require MFA: true

Version published with MFA: true

Links:

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