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rggen 0.26.2

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Gemfile:
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install:
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Versions:

  1. 0.36.0 January 07, 2026 (75.5 KB)
  2. 0.35.2 July 21, 2025 (16 KB)
  3. 0.35.1 June 01, 2025 (16 KB)
  4. 0.35.0 February 19, 2025 (16 KB)
  5. 0.34.0 January 23, 2025 (16 KB)
  6. 0.26.2 June 13, 2022 (15.5 KB)
Show all versions (75 total)

Runtime Dependencies (5):

rggen-core ~> 0.26.0
rggen-default-register-map ~> 0.26.0
rggen-markdown ~> 0.22.0
rggen-spreadsheet-loader ~> 0.21.0
rggen-systemverilog ~> 0.26.1

Development Dependencies (1):

bundler >= 0
Show all transitive dependencies

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

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Total downloads 117,145

For this version 972

Version Released:

License:

MIT

Required Ruby Version: >= 2.6

New versions require MFA: true

Version published with MFA: true

Links:

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