rggen 0.10.0
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map documents.
Gemfile:
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install:
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Runtime Dependencies (3):
Development Dependencies (1):
bundler
>= 0
Owners:
Pushed by:
Authors:
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Taichi Ishitani
SHA 256 checksum:
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